CMOS imagers are known in the art. Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No 6,376,868, U.S. Pat. No 6,310,366, U.S. Pat. No 6,326,652, U.S. Pat. No 6,204,524, and U.S. Pat. No 6,333,205, each assigned to Micron Technology, Inc. The disclosures of the forgoing patents are hereby incorporated by reference in their entirety.
A top-down and cross-sectional view of a typical and exemplary CMOS four-transistor (4T) pixel cell 10 is illustrated in FIGS. 1a and 1b. As it will be described below, the CMOS sensor pixel 10 includes a photoconversion device 12 (e.g., photo-generated charge accumulating area) in a portion of the substrate 14. This area 12 can be a pinned photodiode (FIG. 1b). The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted. It should be understood, however, that the pixel 10 may also typically include a photogate or other image to charge converting device, in lieu of a pinned photodiode, as the initial accumulating area 12 for a photoconversion device.
The pixel 10 of FIG. 1a has a transfer gate 16 for transferring photoelectric charges generated in the charge accumulating region 12 to a floating diffusion region (sensing node) 18. The floating diffusion region 18 is connected 24 to a gate 22 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 26 for selectively gating the output signal to terminal 28. A reset transistor having gate 20 resets the floating diffusion region 18 from a supply voltage applied at a source/drain region 30 between gates 20 and 22 to a specified charge level before each charge transfer from the charge accumulating region 12. The pixel 10 is typically isolated from other like cells of an imager array by shallow trench isolation regions 32. As shown in FIG. 1a, the charge accumulation region 12 of the pixel 10 is somewhat limited in area by the area taken up by the associated pixel circuitry.
A cross-sectional view of the exemplary pixel 10 of FIG. 1a taken along line a-a′ is illustrated in FIG. 1b. The charge accumulating region 12 is formed as a pinned photodiode, which has a photosensitive region or p/n/p junction formed by a p-type layer 34, an n-type region 36 and the underlying p-type substrate 14. The pinned photodiode includes two p-type regions 14, 34 so that the n-type photodiode region 36 is fully depleted at a pinning voltage. The floating diffusion region 18 adjacent the transfer gate 16 and the source/drain region 30 are preferably n-type and are formed in a p-well 40 in the substrate 14. Also shown in FIG. 1b is contact 24, which connects the floating diffusion region 18 with the source follower transistor gate 22 (FIG. 1a at 24) and contact 38, which connects the source/drain region 30 with a voltage supply.
Generally, in CMOS image sensors such as the pixel 10 of FIGS. 1a and 1b, incident light causes electrons to collect in region 36. A maximum output signal, which is produced by the source follower transistor having gate 22, is proportional to the number of electrons to be extracted from the region 36. The maximum output signal increases with increased electron capacitance or acceptability of the region 36 to acquire electrons. The electron capacity of pinned photodiodes typically depends on the doping level of the image sensor and the dopants implanted into the active layer.
CMOS imagers typically suffer from poor signal to noise ratios and poor dynamic range as a result of the inability to fully collect and store the electric charge collected in the region 36. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, it would be desirable for the signal to noise ratio and dynamic range of the pixel to be as high as possible. Additionally, as semiconductor devices are scaled down, more efficient pixel configurations are desirable to maximize photoconversion device size and minimize the area required for the related pixel circuitry.
Silicon-on-insulator (SOI) substrates are increasingly being used in high performance CMOS integrated circuits. For system on chip (SOC) applications that demand a significant amount of logic circuitry, SOI can offer benefits in power efficiency, low parasitic capacitance, and high switching speeds. In SOI technology, a layer of SiO2 (or Si3N4), referred to as the buried oxide (BOX), is beneath an active silicon layer, formed either through a high dose oxygen implantation and subsequent annealing (Separation by Implantation of Oxygen, or SIMOX), or by bonding two oxidized silicon wafers together (BESOI) and then etching-back one of those wafers until a thin layer of silicon remains above the oxide layer where the two wafers had been joined. A CMOS process is typically implemented on these wafers, in which the insulating BOX layer drastically reduces leakage currents, eliminates the problem of latchup (parasitic bipolar action as a result of the n/p/n and p/n/p junctions formed by the various implants used for the CMOS process), and the reduction of RF parasitics, since the devices now sit on an insulating layer. Image sensors could benefit from such advantages over typical substrates; however, integrating an image sensor array into SOI technology has proven difficult.